The present invention relates generally to microcontrollers and, particularly, to the use and management of on-chip non-volatile memory.
Traditionally, microcontrollers that are compatible with the industry standard 8051 architecture assume a memory organized into four address spaces, each with corresponding physical memory circuits. The four address spaces correspond to: internal program code, internal data, external program code and external data. In this context, xe2x80x9cinternalxe2x80x9d means code or data that is stored in controller on-chip memory and xe2x80x9cexternalxe2x80x9d means code or data that is stored in off-chip memory. An illustration of the conventional 8051 memory organization is shown in FIG. 1.
Referring to FIG. 1, the internal program memory 102 is typically implemented as mask-ROM 120 or other non-volatile memory, the internal data memory 106 as 128 or 256 bytes of SRAM plus a special function register (SFR) array 140, and the external program and data memories 104,108 each as up to 64K bytes of SRAM 110, 112. The internal data can be read and written by internal programs or external programs via an internal memory bus. The internal program code, which is read-only, can be fetched over the same internal bus. The external program code, which is read-only, can be fetched over an external bus. The external data can be read and written by external programs or internal programs via the same external bus.
Each area of memory is accessed in response to particular instructions. For example, internal program code is fetched via the internal data bus one byte at a time in response to a move ode (MOVC) instruction, and no other instruction, issued by an internal or external program. The MOVC instruction has two different formats:
Internal and external program code reads are differentiated by the location of the fetched code byte. CPU will detect whether the code is in internal or external program memory and fetch the code accordingly.
Internal data is fetched and written via the internal bus using a wide range of memory access instructions issued by an internal or external program in one of four addressing modes:
External Program code is fetched via the external bus in response to a move code (MOVC) instruction issued by an internal or external program. The MOVC instruction has two different formats:
The external data is fetched and written via the external data bus in response to a move external (MOVX) instruction issued by an external or internal program. The MOVX instruction has 16-bit and 8-bit formats:
For additional information on the MCS-51 family of controllers, please see the publication, xe2x80x9cMCS(copyright)-51 Microcontrollers Family User""s Manual (published by Intel, February, 1994) p. 1-1 to p. 2-75.
Given this architecture, traditional 8051 microcontrollers cannot be used in applications where it is necessary to retain internal data in the absence of a power-supply. This problem has been addressed in the Atmel C51 family of microcontrollers (i.e., the 89S8252 and 89LS8252), which is now described with reference to FIG. 2. Additional information on memory organization and programming in the Atmel C51 family of microcontrollers is provided in the following documents, which are incorporated herein by reference:
(1) xe2x80x9cAT89S8252 Primer,xe2x80x9d Atmel Application Note, Rev. 1018A-03/98; and
(2) xe2x80x9c8-Bit Microcontroller with 8K Bytes Flash, AT89S8252,xe2x80x9d pp. 4-105 to 4-135, Atmel AT89-series Microcontroller Databook, Rev. 0401D-A-12/97.
Referring to FIG. 2, the Atmel C51 family of microcontrollers implements the 8051 memory organization of FIG. 1 using four separate memory circuits 162-168, but uses non-volatile Flash memory 170 for the internal program code memory and non-volatile EEPROM 174 and SRAM 180 for the internal data memory. This arrangement ensures that the internal data can be maintained in the absence of power and can be reprogrammed.
Access to all but the internal data is the same as in the traditional 8051 memory scheme. The internal data SRAM 180 can be accessed using the same range of memory access instructions and access modes described above (register, direct, indirect). Additionally, Atmel allows the internal EEPROM 174 to be accessed through the MOVX instruction which, in the traditional 8051 architecture, is used to access only the external data memory 168. In the Atmel scheme, access to the internal EEPROM 174 via the MOVX instruction is enabled when an EEMEN bit in the special function register (SFR) 190 is set. When the EEMEN bit is cleared, the MOVX instruction accesses the external data memory 168.
The Atmel memory scheme provides non-volatile memory for internal data in a manner that is consistent with the traditional 8051 memory organization scheme and memory access instructions. However, due to the Flash (program) and EEPROM (data) memories 170, 174 being physically distinct, the situation could arise where there is not enough room for internal data storage in the EEPROM 174 even though there is room in the Flash memory 170 (and vice-versa for internal program code storage). As a result, this scheme does not make efficient use of the relatively expensive, on-chip non-volatile memory 170, 174. Also, while data can be stored in the internal program Flash memory, the usefulness of such data is limited as it would be read-only during program execution. Once the data in the program area is programmed it cannot be altered until the whole program is reprogrammed.
Additionally, it is difficult to reprogram the Flash memory 170 to update the programs or data stored therein. This is because the Flash memory 170 can only be reprogrammed on block basis, i.e., updating any byte in the Flash memory requires erasing the entire block first. Among other things, this prevents the Flash memory 170 from being programmed by software executing on the microcontroller or by external devices through the microcontroller""s serial port. Additionally, it would not be practical to program a Flash memory in this byte-by-byte fashion.
Therefore, there is a need for an 805 1-compatible microcontroller that provides on-chip, non-volatile memory for internal data and program code storage in such a manner that all on-chip, non-volatile memory is efficiently utilized. There is also a need for an microcontroller memory scheme that allows internal program code and data stored in the non-volatile memory to be reprogrammed in place by software executing on the microcontroller or by external devices through the microcontroller""s serial port. There is a further need for a microcontroller memory in which data and program code stored in the internal program area is easily accessed and reprogrammed. Finally, there is a need for a memory access scheme for program code and data stored in the non-volatile program area that can be implemented using Flash memory or EEPROM.
In summary, the present invention is a microcontroller memory system that provides on-chip, non-volatile memory for internal data and program code storage in such a manner that all on-chip, non-volatile memory is efficiently utilized. In one embodiment, a microcontroller memory scheme allows internal program code and data stored in the non-volatile memory to be reprogrammed in place by software executing on the microcontroller or by external devices through the microcontroller""s serial port. In another embodiment, data and program code stored in the internal program area can be accessed using any instruction employed to access via an internal data bus the contents of an on-chip, volatile memory used to store internal data.
In any of the embodiments, the non-volatile memory used to store the program code and internal data can be implemented with EEPROM.
A particular embodiment of a microcontroller memory system implemented in accordance with the present invention includes an internal volatile memory and an internal non-volatile memory. In this embodiment, the internal volatile memory is used to store internal data and the internal non-volatile memory is used to store in any proportion internal non-volatile data and/or internal program code. The data and program code are stored in the internal non-volatile memory so as to be accessible to any microcontroller instruction that can access the internal data in the internal volatile memory. In one embodiment, the contents of the non-volatile memory can be programmed by an external device via the microcontroller""s serial port. In another embodiment, the contents of the non-volatile memory can be programmed by software executing on the microcontroller.
One particular embodiment is a virtual memory system for use in a microcontroller with a memory architecture that includes internal data and internal program address spaces, both of which are accessible by data transfer instructions. This embodiment includes a single, internal non-volatile memory configured to store both internal data and internal program code for access via the internal data and internal program code address spaces, respectively.
Another embodiment of the virtual memory system includes, in addition to the internal non-volatile memory, an internal volatile memory that is also configured to store the internal data for access via the internal data address space. Any of the embodiments with both internal volatile and non-volatile data memory can include a special function register with a flag that indicates whether an internal data access is to be into the internal non-volatile memory or the internal volatile memory.
Alternatively, a flag implemented by a special function register bit can indicate whether a data access is into the non-volatile memory or an external volatile data memory. This embodiment supports a set of one or more internal memory access modes and a set of one or more external memory access modes distinct from the internal access modes. When the flag indicates that a data access is to be into the volatile memory, the data access is into the internal volatile memory when a program executing on the microcontroller employs one of the internal memory access modes and into the external memory when the program employs one of the external access modes.